Isolate generic system level failures into a more focused area of the platform or CPU Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Devise validation strategy from pre silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams

Design of complex building blocks of a PLL including architecture development and transistor level circuit design Run pre tapeout verification flows to confirm design meets performance, power, reliability and timing requirements. Work closely with mask design engineers to deliver the physical design as well as define production/bench level test plans with post silicon cha

Provide advisement and coordination for RPPG leadership team to drive decision making processes and execution of the strategic business objectives. Develop collaterals (presentations, pre reads, communications) for the CVP on internal and external activities through original contribution and/or collaboration with executives and senior leaders across RPPG. Represent the CV